library ieee;
use ieee.std_logic_1164.all;

ENTITY compare_logic is

PORT (clock, enable, reset: IN STD_LOGIC;
      input,checkaddress: IN STD_LOGIC_VECTOR(47 downto 0);
      current: OUT STD_LOGIC_VECTOR(47 downto 0);
      z: OUT STD_LOGIC
);
END compare_logic;    

architecture structural of compare_logic is

signal regvalue: STD_LOGIC_VECTOR(47 downto 0);

component registerlatch IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (47 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (47 DOWNTO 0)
	);
END component;

begin 

register1: registerlatch port map(clock, input, enable, reset, regvalue);

z<=	(checkaddress(0) XNOR regvalue(0)) AND 
	(checkaddress(1) XNOR regvalue(1)) AND
	(checkaddress(2) XNOR regvalue(2)) AND
	(checkaddress(3) XNOR regvalue(3)) AND  
	(checkaddress(4) XNOR regvalue(4)) AND 
	(checkaddress(5) XNOR regvalue(5)) AND
	(checkaddress(6) XNOR regvalue(6)) AND
	(checkaddress(7) XNOR regvalue(7)) AND
	(checkaddress(8) XNOR regvalue(8)) AND
	(checkaddress(9) XNOR regvalue(9)) AND
	(checkaddress(10) XNOR regvalue(10)) AND
	(checkaddress(11) XNOR regvalue(11)) AND
	(checkaddress(12) XNOR regvalue(12)) AND
	(checkaddress(13) XNOR regvalue(13)) AND
	(checkaddress(14) XNOR regvalue(14)) AND
	(checkaddress(15) XNOR regvalue(15)) AND
	(checkaddress(16) XNOR regvalue(16)) AND
	(checkaddress(17) XNOR regvalue(17)) AND
	(checkaddress(18) XNOR regvalue(18)) AND
	(checkaddress(19) XNOR regvalue(19)) AND
	(checkaddress(20) XNOR regvalue(20)) AND
	(checkaddress(21) XNOR regvalue(21)) AND
	(checkaddress(22) XNOR regvalue(22)) AND
	(checkaddress(23) XNOR regvalue(23)) AND
	(checkaddress(24) XNOR regvalue(24)) AND
	(checkaddress(25) XNOR regvalue(25)) AND
	(checkaddress(26) XNOR regvalue(26)) AND
	(checkaddress(27) XNOR regvalue(27)) AND
	(checkaddress(28) XNOR regvalue(28)) AND
	(checkaddress(29) XNOR regvalue(29)) AND
	(checkaddress(30) XNOR regvalue(30)) AND
	(checkaddress(31) XNOR regvalue(31)) AND
	(checkaddress(32) XNOR regvalue(32)) AND
	(checkaddress(33) XNOR regvalue(33)) AND
	(checkaddress(34) XNOR regvalue(34)) AND
	(checkaddress(35) XNOR regvalue(35)) AND
	(checkaddress(36) XNOR regvalue(36)) AND
	(checkaddress(37) XNOR regvalue(37)) AND
	(checkaddress(38) XNOR regvalue(38)) AND
	(checkaddress(39) XNOR regvalue(39)) AND
	(checkaddress(40) XNOR regvalue(40)) AND
	(checkaddress(41) XNOR regvalue(41)) AND
	(checkaddress(42) XNOR regvalue(42)) AND 
	(checkaddress(43) XNOR regvalue(43)) AND
	(checkaddress(44) XNOR regvalue(44)) AND
	(checkaddress(45) XNOR regvalue(45)) AND
	(checkaddress(46) XNOR regvalue(46)) AND
	(checkaddress(47) XNOR regvalue(47));
	
	
current<= regvalue;

end structural;
